1. Field of the Invention
The invention relates to the area of semiconductor integrated circuits, particularly to a data sampling device for a memory device, and a sampling controller.
2. Description of Related Art
A memory is an essential part of a processor, its main function is to provide a storage space for data, e.g., programs, original data, interim results, and operation results for the processor. The memory either functions as an area in which the processor runs programs, or communicates with external devices in coordination with the processor. Thus, the memory is required to possess features of high capacity, high speed, and high reliability.
A high speed memory transmits data both at the rising edge and the falling edge of a clock period. That is, the memory works twice during one clock cycle. As the effective time length for each sample of data is very short at high frequency clock, the memory requires a sampling circuit to be synchronized with high accuracy. The performance of the sampling circuit may dictate the reliability of the memory. Accordingly, the design of a sampling circuit for high frequency clock hence high transmission rate of data becomes an essential part in memory designs.
FIG. 1 shows a conventional sampling device of a memory chip. The sampling device of the memory carries out data sampling in a synchronized manner. The sampling device includes a sampling controller and a memory chip. The sampling controller includes three tri-state gate units PMEMIO, PMEMIO1 and PMEMIO2, and two register units DQ_S1 and DQ_S2. The tri-state gate unit PMEMIO includes three ports I, C and PAD. Signals are inputted to the port I of the tri-state gate unit PMEMIO and then outputted from the port PAD of the tri-state gate unit PMEMIO. The tri-state gate unit PMEMIO1 includes three ports I1, C1, and PAD1. Signals are inputted to the port PAD1 of the tri-state gate unit PMEMIO1 and outputted from the port C1 of the tri-state gate unit PMEMIO1. The tri-state gate unit PMEMIO2 includes three ports I2, C2, and PAD2. Signals are inputted to the port PAD2 of the tri-state gate unit PMEMIO2 and outputted from the port C2 of the tri-state gate unit PMEMIO2. The memory chip includes an input port CK for a clock signal, a data output port DQN, and an output port DQS for a sampling clock signal.
After being inverted in phase by a controller, a clock DCLK is provided to the port I of the tri-state gate unit PMEMIO and outputted from the port PAD, and then functions as an operational clock signal to the memory chip. The data output port DQN outputs data, typically experiencing a signal delay. The data is provided to the tri-state gate unit via the port PAD1 of the tri-state gate unit PMEMIO1 and then provided to the register unit DQ_S1 via the port C1. Meanwhile, a sampling clock signal from the DQS is provided to the tri-state gate unit via the port PAD2 of the tri-state gate unit PMEMIO2 and then outputted to a clock port CK1 of the register unit DQ_S1 from the port C2. The sampling controller samples the data coming into the register unit DQ_S1 and saves effective data in one clock cycle to the register unit DQ_S1. Meanwhile, the sampling controller supplies the clock DCLK to a sampling clock port CK2 of the register unit DQ_S2 and employs the clock DCLK as the sampling clock of the register unit DQ_S2 to sample data recorded in the register unit DQ_S1 and synchronize the sampled data with the clock of the register unit DQ_S2. As such, the data sampling in synchronized manner is finished.
It can be perceived from the above described operation that delay of the memory chip and read-write delay of the input/output port of the controller could cause a phase difference between the register unit DQ_S1 and the register unit DQ_S2. Thus, the synchronous data sampling device needs to pre-estimate the potential maximum delay and then calculate the phase difference based on the delay. In this way, the clock signals of the register unit DQ_S1 and the register unit DQ_S2 are synchronized according to the phase difference so as to ensure the accuracy of the data sampling. However, temperature variation and external electromagnetic interference may enlarge the read-write delays of the memory chip as well as the input/output port of the controller, the factual phase difference between the clock signals of the register unit DQ_S1 and the register unit DQ_S2 may be also enlarged. If the factual phase difference is greater than the pre-estimated phase difference, the register unit DQ_S2 would not properly read the effective data from the register unit DQ_S1, thus mishandling the sampling and decreasing the reliability of the sampling device of the memory.